Alternatives and similar repositories for RV32I-GPU

Users that are interested in RV32I-GPU are comparing it to the libraries listed below

• avl-bsuir / rv64x-base
  Open source GPU extension for RISC-V
  ☆63Updated 4 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆89Updated this week
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆111Updated last month
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated last week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 10 months ago
• OpenXiangShan / nexus-am
  ☆36Updated last week
• riscv / riscv-aia
  ☆96Updated 3 weeks ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆59Updated 10 months ago
• openhwgroup / core-v-sw
  Main Repo for the OpenHW Group Software Task Group
  ☆17Updated 6 months ago
• riscv-admin / graphics
  Graphics SIG organizational information
  ☆39Updated last year
• riscvarchive / riscv-CMOs
  ☆90Updated 3 weeks ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆129Updated this week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated 3 weeks ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆48Updated this week
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆62Updated 9 months ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated 2 weeks ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆294Updated 7 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated 2 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated 3 weeks ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆66Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 3 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆57Updated last year
• riscv / riscv-plic-spec
  PLIC Specification
  ☆147Updated 3 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆65Updated 7 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆283Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆84Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆117Updated this week
• RISCVtestbed / rvv-rollback
  Translate RISC-V Vector Assembly from v1.0 to v0.7
  ☆34Updated last year
• riscv-non-isa / riscv-semihosting
  ☆32Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆193Updated last month