jtgebert / fpganes_release
Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog
☆49Updated 7 years ago
Alternatives and similar repositories for fpganes_release:
Users that are interested in fpganes_release are comparing it to the libraries listed below
- NES in Verilog☆192Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- miniSpartan6+ (Spartan6) FPGA based MP3 Player☆27Updated 5 years ago
- An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA☆70Updated 2 years ago
- Wishbone interconnect utilities☆38Updated last month
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆51Updated last year
- Small (Q)SPI flash memory programmer in Verilog☆59Updated 2 years ago
- UART 16550 core☆33Updated 10 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Test for video output using the ADV7513 chip on a de10 nano board☆50Updated 6 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Documentation and tools related to DECA FPGA board☆21Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆75Updated 11 months ago
- IBM PC Compatible SoC for a commercially available FPGA board☆68Updated 8 years ago
- Verilog Driver for the ILI9341 TFT Module☆22Updated 3 years ago
- FPGA GPU design for DE1-SoC☆73Updated 3 years ago
- Video Stream Scaler☆40Updated 10 years ago
- PCI bridge☆18Updated 10 years ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆30Updated 2 years ago
- Sata 2 Host Controller for FPGA implementation☆13Updated 7 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆88Updated 4 years ago
- Portable HyperRAM controller☆54Updated 3 months ago
- ☆37Updated 3 years ago
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆120Updated this week
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated 10 months ago
- ☆129Updated 3 months ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆76Updated 4 years ago
- Source code to accompany https://timetoexplore.net☆62Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- MIPI DSI transmitter core for Xilinx FPGAs (work in progress)☆81Updated 7 years ago