☆32Apr 24, 2023Updated 2 years ago
Alternatives and similar repositories for Mastering-the-FreeRTOS-Real-Time-Kernel-CN
Users that are interested in Mastering-the-FreeRTOS-Real-Time-Kernel-CN are comparing it to the libraries listed below
Sorting:
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- ☆10Mar 7, 2020Updated 6 years ago
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- 用于解析GPS模块的 $XXRMC 类型数据，并放到结构体中， 依赖 C语言标准库☆10May 26, 2022Updated 3 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- ☆10Oct 11, 2020Updated 5 years ago
- 蓝牙协 议文档大全☆11Aug 14, 2014Updated 11 years ago
- ☆10Oct 18, 2024Updated last year
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆42May 2, 2019Updated 6 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- 插件式系统框架☆11Jun 30, 2015Updated 10 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- mechatronics firmware☆13Apr 14, 2025Updated 10 months ago
- Time management library for embedded devices☆12Apr 21, 2019Updated 6 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆12Mar 20, 2023Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- Code repository for my articles on blogs.embarcadero.com and pythongui.org.☆13Feb 6, 2025Updated last year
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆14Sep 5, 2023Updated 2 years ago
- ☆14Jan 22, 2026Updated last month
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 9 years ago
- Exercism exercises in Tcl.☆11Mar 1, 2026Updated last week
- Smartboard simulation to use a laser pointer as marker/pen. No additional hardware is required, as it works with an ordinary webcam. Emgu…☆13Sep 9, 2016Updated 9 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆15Feb 16, 2024Updated 2 years ago
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆18Nov 18, 2025Updated 3 months ago
- 这是一个pc端的聊天室。☆10May 16, 2021Updated 4 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- Google Voice IM-like client☆17Jan 24, 2014Updated 12 years ago
- GSI Timing Gateware and Tools☆14Feb 25, 2026Updated last week
- Sketches and Python scripts for interacting with Arduino Nano BLE Sense☆12Jul 19, 2020Updated 5 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- Converts provided SVG to bitmap and slices it into tiles for use e.g. in Leaflet. Supports UTFGrid.☆23Apr 15, 2016Updated 9 years ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago