simonayzman / DarknetLinks
An MMORPG proof of concept for Hunter College Capstone - Spring 2015.
☆12Updated 7 years ago
Alternatives and similar repositories for Darknet
Users that are interested in Darknet are comparing it to the libraries listed below
Sorting:
- FPGA Low latency 10GBASE-R PCS☆12Updated 2 years ago
- Simple single cycle RISC processor written in Verilog☆49Updated 7 years ago
- This is a TS class allowing you to interface with amqp lib☆11Updated 3 years ago
- learning VHDL☆12Updated 11 years ago
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆150Updated 9 years ago
- Python tools for Vivado Projects☆72Updated 6 years ago
- Designed a RISC processor with 16 bit instruction set, 4-stage pipeline and a non-pre-emptive interrupt handler. Implemented it in VHDL a…☆19Updated 11 years ago
- VHDL Samples☆70Updated 13 years ago
- A litecoin scrypt miner implemented with FPGA on-chip memory.☆291Updated 11 years ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆29Updated 2 months ago
- A book on using the Spartan 3E FPGA with VHDL, using the Papilio One or Digilent Basys2 boards☆272Updated 11 years ago
- Simple, zero-copy DMA to/from userspace.☆80Updated 2 years ago
- Public repository for Litefury & Nitefury☆313Updated last year
- A pipelined RISCV implementation in VHDL☆96Updated 7 years ago
- ☆28Updated 4 years ago
- Algorithm to hardware compilation tools (e.g. C to VHDL).☆43Updated 2 months ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆72Updated 9 years ago
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆202Updated 7 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆126Updated 9 years ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆23Updated 7 years ago
- ☆14Updated 6 years ago
- Public repository for PicoEVB (Xilinx Artix XC7A50T based)☆266Updated 2 months ago
- Caribou: Distributed Smart Storage built with FPGAs☆68Updated 7 years ago
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆176Updated 4 years ago
- Bitcoin miner for Xilinx FPGAs☆99Updated 12 years ago
- Verilog code for a circuit implementation of Radix-2 FFT☆27Updated 4 years ago
- MIPS processor designed in VHDL☆56Updated 10 years ago
- Simple hash table on Verilog (SystemVerilog)☆51Updated 9 years ago
- Automatically generates analog circuits using evolutionary algorithms☆262Updated 13 years ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Updated 7 years ago