aksy1999 / graduate_cv_templateView external linksLinks
Latex template for Amit Yadav's CV
☆22Oct 23, 2021Updated 4 years ago
Alternatives and similar repositories for graduate_cv_template
Users that are interested in graduate_cv_template are comparing it to the libraries listed below
Sorting:
- An open source 3GPP LTE implementation. (GitHub import of https://sourceforge.net/projects/openlte/)☆10Mar 7, 2017Updated 8 years ago
- Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB☆11Sep 30, 2020Updated 5 years ago
- Benchmark workloads of Nightcore☆12Feb 15, 2021Updated 5 years ago
- ☆10Jan 4, 2026Updated last month
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- In this project, the simulation of simple digital hearing aid was developed using MATLAB programming language. The implementation of this…☆10Nov 11, 2021Updated 4 years ago
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- High-Performance Reproducible BLAS using posit arithmetic☆12Mar 16, 2022Updated 3 years ago
- ☆19Nov 23, 2022Updated 3 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Aug 2, 2019Updated 6 years ago
- A simple utility for doing RISC-V HPM perf monitoring.☆18May 8, 2017Updated 8 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- ☆16Jul 27, 2022Updated 3 years ago
- µTune: Auto-Tuned Threading for OLDI Microservices☆14Oct 8, 2018Updated 7 years ago
- ☆14May 13, 2022Updated 3 years ago
- Matrix Multiply and Accumulate unit written in System Verilog☆13Feb 7, 2019Updated 7 years ago
- DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-c…☆10Dec 7, 2023Updated 2 years ago
- 8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving…☆14Jul 21, 2022Updated 3 years ago
- Hardware designs for fault detection☆19Apr 13, 2020Updated 5 years ago
- Implementation of an Artificial Neural Network (ANN) on FPGA using VHDL☆13Jun 22, 2016Updated 9 years ago
- 32-bit RISC-V based processor with memory controler☆16Sep 2, 2022Updated 3 years ago
- HW/SW co-designed end-host RPC stack☆20Oct 28, 2021Updated 4 years ago
- ☆15Apr 3, 2020Updated 5 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- SRAM macros created for the GF180MCU provided by GlobalFoundries.☆19Apr 10, 2023Updated 2 years ago
- A simple 5-stage Pipeline RISC-V core☆19Jun 8, 2021Updated 4 years ago
- RPerf: Accurate Latency Measurement Framework for RDMA☆15Sep 24, 2025Updated 4 months ago
- ☆14Oct 27, 2020Updated 5 years ago
- ☆19Dec 22, 2025Updated last month
- Recursive unified ORAM☆15Sep 23, 2015Updated 10 years ago
- ☆19Mar 30, 2021Updated 4 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆21May 27, 2024Updated last year
- first-order deep learning accelerator model☆22Nov 27, 2017Updated 8 years ago
- ☆19Oct 18, 2017Updated 8 years ago
- PYNQ demo as seen at FPL 2018☆22Nov 23, 2020Updated 5 years ago
- PYNQ-ZU, AUP UltraScale+ MPSoC academic board☆28Oct 6, 2025Updated 4 months ago
- A Python repository for finding the densest subgraph in a undirected graph☆17Dec 30, 2020Updated 5 years ago
- An set of example implementations which shows how to serialize gRPC messages in JSON☆22Feb 27, 2018Updated 7 years ago
- configuration evolution dataset☆18Feb 25, 2021Updated 4 years ago