Alternatives and similar repositories for Useful-Academic-Links:

Users that are interested in Useful-Academic-Links are comparing it to the libraries listed below

• mikinty / Hardware-Engineer-Interview-Questions
  For aspiring hardware engineers out there.
  ☆58Updated 2 years ago
• vedic-partap / Computer-Organization-and-Architecture-LAB
  Solution to COA LAB Assgn, IIT Kharagpur
  ☆35Updated 6 years ago
• Ashwin-op / IIITDMK_Courses_Repositories
  A collection of course repositories of IIITDM Kancheepuram students
  ☆26Updated 4 years ago
• rajesh-s / computer-architecture-and-systems-resources
  A curated list of Computer Architecture and Systems resources
  ☆488Updated last month
• Rit-ctrl / Resources
  Resources
  ☆13Updated 3 years ago
• SinghCoder / Icarus_Verilog
  This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
  ☆52Updated 3 years ago
• digital-design-hq / Digital-Resources
  ☆54Updated 3 years ago
• UtkarshPathrabe / Computer-Architecture-Lab-Solutions-BITS-Pilani
  Contains the Lab Sheets and their Solutions of the Computer Architecture Course in BITS Pilani
  ☆17Updated last year
• seifhelal / Cache-Simulator
  A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memo…
  ☆19Updated 7 years ago
• cserl-iitb / bootcamp2022
  The repo for all content related to Bootcamp 2022.
  ☆40Updated 2 years ago
• SubZer0811 / VLSI
  All the projects and assignments done as part of VLSI course.
  ☆18Updated 4 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆145Updated 2 years ago
• 0xd3ba / build-your-own-prefetcher
  This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator
  ☆35Updated 3 years ago
• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆194Updated 2 years ago
• MPSLab-ASU / ML-Accelerators
  Topics in Machine Learning Accelerator Design
  ☆67Updated 2 years ago
• lastweek / fpga_readings
  Recipe for FPGA cooking
  ☆291Updated 4 months ago
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆64Updated this week
• CMU-HKN / CMU-ECE-CS-Guide
  How to survive CMU as an ECE/CS major
  ☆537Updated 7 months ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆190Updated 3 weeks ago
• 61c-teach / sp22-lab-starter
  ☆14Updated 2 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆73Updated 11 months ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆199Updated 4 years ago
• xmpf / awesome-risc-v
  Curated list of awesome resources related with RISC-V
  ☆72Updated 2 years ago
• aklsh / getting-started-with-verilog
  Verilog modules for beginners
  ☆24Updated 2 years ago
• Adhesh148 / BaBbLe
  A simple chat room application built using socket programming concepts and TCP protocol. The client-side UI is made using PyQt5.
  ☆9Updated 4 years ago
• SubZer0811 / verilog_grapher
  Graph your gate-level verilog code as a directed graph!
  ☆16Updated 4 years ago
• ChampSim / ChampSim
  ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture …
  ☆557Updated last week
• hyerania / Belady-Cache-Replacement
  Using Belady's algorithm for improved cache replacement
  ☆43Updated 5 years ago
• thesrsakabuvttchi / VLIW
  This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction schedulin…
  ☆16Updated 3 years ago
• CMU-SAFARI / ramulator2
  Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …
  ☆280Updated 2 months ago