phoulx / nju-os-workbenchView external linksLinks
南大2024操作系统课程实验
☆28Mar 9, 2025Updated 11 months ago
Alternatives and similar repositories for nju-os-workbench
Users that are interested in nju-os-workbench are comparing it to the libraries listed below
Sorting:
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- https://jyywiki.cn/OS/2024/ 操作系统：设计与实现 (2024 春季学期) JYY的所有课程实例代码☆14May 21, 2024Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- NJU oslab 南京大学操作系统大班实验☆27Jan 22, 2024Updated 2 years ago
- ☆12Aug 12, 2022Updated 3 years ago
- NUDT 高级体系结构实验☆35Sep 21, 2024Updated last year
- NJUCS 2023 Spring DLCO 南京大学 数字逻辑与计算机组成 课程实验☆30Mar 5, 2025Updated 11 months ago
- ☆12Sep 2, 2023Updated 2 years ago
- 大R杂货 迷你OpenWrt 4G 随身WiFi MagicBox AC750 双频路由 QCA9531+9887☆13Jul 4, 2022Updated 3 years ago
- Inverse Quantum-Optical Design of High-Dimensional Qudits☆17Aug 2, 2022Updated 3 years ago
- ☆10Jun 23, 2023Updated 2 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- NJU 操作系统: 设计与实现☆99Sep 25, 2022Updated 3 years ago
- ☆10Jul 19, 2020Updated 5 years ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆14Feb 26, 2025Updated 11 months ago
- Padavan for MI-R3G☆10Jul 18, 2018Updated 7 years ago
- simple 4-BIT CPU with 74-serials chip，origin by Kaoru Tonami in his book “How to build a CPU”☆14Oct 19, 2024Updated last year
- 2023年电赛E题上位机视觉算法☆14May 23, 2024Updated last year
- A Flexible Cache Architectural Simulator☆16Sep 16, 2025Updated 5 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- Works for Applied Deep Learning / Machine Learning and Having It Deep and Structured (2017 FALL) @ NTU☆11Aug 14, 2018Updated 7 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆11Jan 17, 2024Updated 2 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Aug 17, 2019Updated 6 years ago
- ntablet_documents☆10May 30, 2020Updated 5 years ago
- Automatically exported from code.google.com/p/byte-unixbench☆10Mar 17, 2018Updated 7 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- A python library for ngspice☆14Jun 21, 2022Updated 3 years ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- Python program that generates the hologram of a phase-only SLM to produce a desired (phase and amplitude) mode profile, as described in h…☆11Jun 23, 2020Updated 5 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- ☆16Jan 18, 2025Updated last year
- 基于tp5的gateway扩展☆12Aug 21, 2023Updated 2 years ago
- Pipelined 64-bit RISC-V core☆15Mar 7, 2024Updated last year
- 中国科学技术大学龙芯杯参赛作品仓库合集☆16Oct 2, 2024Updated last year
- A LevelDB for implementing LSM-related papers☆11Aug 7, 2023Updated 2 years ago
- Sifive All Aboard 系列文章翻译☆11Nov 26, 2021Updated 4 years ago
- Architect's workbench☆10May 5, 2016Updated 9 years ago
- Digital system design: Training lessons and exercise projects for students☆11May 12, 2023Updated 2 years ago