Alternatives and similar repositories for data-structures-and-algorithms

Users that are interested in data-structures-and-algorithms are comparing it to the libraries listed below

• mortbopet / Ripes
  A graphical processor simulator and assembly editor for the RISC-V ISA
  ☆2,971Updated 2 months ago
• alfadelta10010 / COD-Lab
  Instructions & Assignments for COD Lab - UE22EC352A
  ☆4Updated 7 months ago
• gigahidjrikaaa / Engineering-Books
  Softcopy of Engineering Books. If you want a book{s} to be taken down, please contact me.
  ☆479Updated last year
• emrealci / FPGA-Verilog
  Practices related to the fundamental level of the programming language Verilog.
  ☆11Updated 2 years ago
• BrunoLevy / learn-fpga
  Learning FPGA, yosys, nextpnr, and RISC-V
  ☆2,842Updated 4 months ago
• yusfux / KASIRGA-GUN
  KASIRGA-GUN | RV32IMCX
  ☆11Updated 10 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,496Updated 3 years ago
• MPA-MLF / Exercises
  Lab files of Machine Learning Fundamentals course taught at the Brno University of Technology
  ☆10Updated 4 months ago
• m3y54m / FPGA-ASIC-Roadmap
  A roadmap for those who want to build a career as an FPGA / ASIC Engineer
  ☆356Updated 7 months ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,569Updated last year
• ShawnHymel / introduction-to-rtos
  ☆557Updated 4 months ago
• MrCroesus / MMv3
  ☆16Updated 6 months ago
• logisim-evolution / logisim-evolution
  Digital logic design tool and simulator
  ☆5,902Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,817Updated last week
• Teoria-de-Circuitos-II / TC2Lib--LTSPICE
  Biblioteca LTSpice
  ☆12Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,611Updated last month
• jaspreetsingh009 / ADC_LCD_FPGA
  ADC & LCD Interfacing using Verilog & VHDL
  ☆12Updated 8 years ago
• jihadsamarji / Ball-Plate-Control
  This is a project done for a Master Thesis in the Electromechanical Engineering (specialization: Mechatronics), it is about the design an…
  ☆11Updated last year
• riscv / learn
  Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
  ☆943Updated 5 months ago
• aseddin / ece_3300
  ECE 3300 HDL Code
  ☆49Updated 2 years ago
• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆595Updated 8 months ago
• mikinty / Hardware-Engineer-Interview-Questions
  For aspiring hardware engineers out there.
  ☆69Updated 3 months ago
• abdelazeem201 / ASIC-Design-Roadmap
  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…
  ☆359Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,053Updated 3 years ago
• ensariskin / 5-Stage-Pipeline-RV32I
  5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set
  ☆10Updated 2 years ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆380Updated 10 months ago
• GabrielEValenzuela / MicrocontrollerExamples
  Example projects for LPC1769 and STM32 microcontrollers. Includes code samples and setup instructions for various functionalities and per…
  ☆10Updated 7 months ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆971Updated 2 weeks ago
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,540Updated last week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,136Updated last month