NREL FASTv8, with MATLAB GUI and Simulink integration
☆38Sep 16, 2026Updated 3 weeks ago
Alternatives and similar repositories for FASTTool
Users that are interested in FASTTool are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Support for modular development with Simulink models☆15Jan 18, 2022Updated 4 years ago
- A standard test method library for the Advantest V93000 (and hopefully others in future)☆16Jul 22, 2022Updated 4 years ago
- A project demonstrate how to config ad9361 to TX mode☆13Dec 9, 2018Updated 7 years ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 9 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- delphi7-lite 单文件版本☆12Jun 22, 2020Updated 6 years ago
- zprint in Emacs☆10Jun 13, 2021Updated 5 years ago
- Time management library for embedded devices☆14Apr 21, 2019Updated 7 years ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- Move/swap things more conveniently in Emacs☆12Sep 26, 2018Updated 8 years ago
- Source code for 'JavaFX 9 by Example' by Carl Dea, Gerrit Grunwald, José Pereda, Sean Phillips, and Mark Heckler☆11Nov 3, 2017Updated 8 years ago
- A picorv32 RISC-V processor with some very simple memory and peripherals. For Terasic DE-0 Nano☆13Apr 15, 2019Updated 7 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- Mark current symbol and jump in all matching symbols.☆13Jan 5, 2019Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- petiger的版本发布☆12Dec 3, 2020Updated 5 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆13Jul 14, 2024Updated 2 years ago
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 10 years ago
- Making Lattice SensAI work properly on tinyVision products☆13Nov 22, 2022Updated 3 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆17Aug 24, 2024Updated 2 years ago
- ☆12Oct 18, 2024Updated last year
- Code repository for my articles on blogs.embarcadero.com and pythongui.org.☆13Feb 6, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 7 months ago
- my org files publish by GNU/Emacs org-mode .☆14Sep 10, 2021Updated 5 years ago
- ☆14Jul 20, 2026Updated 2 months ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 8 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 11 years ago
- 一个基于scrapy+selenium+phantomjs的爬虫程序，用于抓取多个学校的学术报告信息☆10Sep 3, 2015Updated 11 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- The source code for the XTRX FPGA image☆17Nov 19, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- C#版本的word,excel操作程序☆10Dec 4, 2015Updated 10 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- SystemVerilog code for image processing tasks like demosaicing☆11Jun 28, 2020Updated 6 years ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆15Jun 1, 2017Updated 9 years ago
- P4 compatible HLS modules☆11Apr 23, 2018Updated 8 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago