MP3 Player developed on FPGA(DIGILENT NEXYS 4 DDR)
☆16Feb 11, 2019Updated 7 years ago
Alternatives and similar repositories for mp3-player
Users that are interested in mp3-player are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 同济大学数字逻辑课程期末大作业☆65Sep 5, 2021Updated 4 years ago
- 同济大学数字逻辑大作业,基于OLED显示屏、MP3播放器和PS/2键盘的电子琴☆20Jan 7, 2022Updated 4 years ago
- 同济计科大三下操作系统+计算机图形学+计网+系统结构+软工复习☆22Jan 2, 2025Updated last year
- 数字逻辑期末大作业,7k下落式音乐游戏☆43Feb 6, 2023Updated 3 years ago
- 数字逻辑大作业:FPGA的电子琴,基于Nexys 4板,采用Verilog实现☆21Sep 28, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 同济大学 数据库课设 TJU Database Curriculum Project☆11May 30, 2020Updated 5 years ago
- Greedy Snake game on Nexys 4 DDR with Verilog.☆30Jul 15, 2022Updated 3 years ago
- Ethernet MAC for the Digilent Nexys 4 DDR FPGA.☆31Aug 21, 2018Updated 7 years ago
- 同济大学 数字逻辑+汇编+数据结构作业及项目+人工智能导论笔记+形式语言与自动机笔记+计算机组成原理小作业+编译原理+编译原理课程设计+计算机网络+操作系统课程设计+数据库课程设计+计算机系统结构课程设计+人机交互导论+软件工程+Web技术+深度学习与神经网络+数据库系统原…☆343Mar 18, 2025Updated last year
- 同济大学22级数字逻辑大作业☆33Nov 18, 2025Updated 6 months ago
- 2017秋季学期计组实验,含54条单周期CPU☆28Dec 3, 2018Updated 7 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- A small Lua formatter / pretty printer☆12Nov 25, 2020Updated 5 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK☆16Dec 2, 2018Updated 7 years ago
- 2024年同济大学计算机网络实验课个人实验二☆10Jun 26, 2024Updated last year
- ALINX ALTERA FPGA黑金开发学习板 CYCLONE IV 数电课设八位模型机☆13Jul 27, 2018Updated 7 years ago
- Codes for our paper "AgentMonitor: A Plug-and-Play Framework for Predictive and Secure Multi-Agent Systems"☆13Dec 13, 2024Updated last year
- 同济大学计算机部分作业,计算机系统实验(系统移植参考github上学长的代码),操作系统课程设计,数据库课程设计,web技术,编译原理(不包含两次实验,因为是小组作业hhh),操作系统,计算机系统结构(流水线CPU,静态的和动态的),计算机组成原理(包含31条MIPS单周期…☆128Mar 31, 2025Updated last year
- UVA-Human-Skeleton-Preprocessing☆10May 4, 2023Updated 3 years ago
- OpenVDB renderer using OpenGL☆15May 14, 2021Updated 5 years ago
- 同济23数字逻辑张冬冬老师作业☆11Nov 23, 2024Updated last year
- Project for CS101016 and CS100160, Tongji University. Use Verilog HDL to build a CPU.☆10Mar 20, 2021Updated 5 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- 同济大学计算机科学与技术、信息安全专业课程资源共享仓库。含部分科目介绍、报告模板、实验工具等内容。期待更多课程加入……☆416Mar 7, 2026Updated 2 months ago
- a FPGA tank game for ZJU Digital logic design☆10Jan 17, 2021Updated 5 years ago
- Official release of code for the paper RL is a hammer and LLMs are nails A simple RL approach to stronger prompt injection attacks☆48May 6, 2026Updated 2 weeks ago
- iLLaVA: An Image is Worth Fewer Than 1/3 Input Tokens in Large Multimodal Models (ICLR2026)☆22Mar 29, 2026Updated last month
- Source code for "Distraction-based Neural Models for Document Summarization" runnable on GPU and CPU.☆15May 22, 2018Updated 8 years ago
- Boost library subset for FireBreath☆13Apr 17, 2017Updated 9 years ago
- [NeurIPS 2025] Official repository for “FlowCut: Rethinking Redundancy via Information Flow for Efficient Vision-Language Models”☆32Dec 9, 2025Updated 5 months ago
- CNN Implemetation on ZYNQ-7010☆25Sep 24, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 本项目是利用Faster-RCNN算法对目标进行识别与分类。深度学习框架是MXNet,迁移训练和fine-tuning的模型是VGG16和ResNet-101两个模型。语言是python和pyqt。用pyqt简单的做了一个操作界面。界面如图show.png所示☆13Dec 22, 2019Updated 6 years ago
- Nexys 4 DDR Artix-7☆11Jun 15, 2018Updated 7 years ago
- Benchmarking data and script used for LLM multi-agent collaboration systems from AWS Bedrock Agents Science team.☆19Dec 10, 2024Updated last year
- 龙芯官方给出的MIPS源码与我个人优化文件结构之后的源码☆15May 3, 2019Updated 7 years ago
- ☆11Dec 13, 2014Updated 11 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- Some design examples of Verilog about digital circuits☆30Nov 21, 2020Updated 5 years ago