MP3 Player developed on FPGA(DIGILENT NEXYS 4 DDR)
☆16Feb 11, 2019Updated 7 years ago
Alternatives and similar repositories for mp3-player
Users that are interested in mp3-player are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 使用C++和EasyX绘图库编写的经典贪吃蛇范例游戏。☆11Oct 11, 2017Updated 9 years ago
- 同济大学数字逻辑大作业，基于OLED显示屏、MP3播放器和PS/2键盘的电子琴☆20Jan 7, 2022Updated 4 years ago
- 同济大学数字逻辑大作业☆31Jan 18, 2022Updated 4 years ago
- 数字逻辑大作业：FPGA的电子琴，基于Nexys 4板，采用Verilog实现☆22Sep 28, 2019Updated 7 years ago
- 同济大学 数据库课设 TJU Database Curriculum Project☆10May 30, 2020Updated 6 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Greedy Snake game on Nexys 4 DDR with Verilog.☆31Jul 15, 2022Updated 4 years ago
- Ethernet MAC for the Digilent Nexys 4 DDR FPGA.☆30Aug 21, 2018Updated 8 years ago
- Review for Course 100396,Tongji Uni.☆40Mar 13, 2022Updated 4 years ago
- 同济计科大三下操作系统+计算机图形学+计网+系统结构+软工复习☆24Oct 15, 2026Updated 2 weeks ago
- A simple PDM microphone interface on FPGA☆15Jan 16, 2022Updated 4 years ago
- 同济计科操作系统、计算机系统机构、计算机网络笔记整理☆25Jun 28, 2025Updated last year
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- 同济大学 数字逻辑+汇编+数据结构作业及项目+人工智能导论笔记+形式语言与自动机笔记+计算机组成原理小作业+编译原理+编译原理课程设计+计算机网络+操作系统课程设计+数据库课程设计+计算机系统结构课程设计+人机交互导论+软件工程+Web技术+深度学习与神经网络+数据库系统原…☆363Mar 18, 2025Updated last year
- 💡同济大学计算机科学与技术专业本科课程资源仓库☆260Sep 25, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Explanation of FPGA code for 8 PDM microphones in Matrix Creator☆15Nov 9, 2020Updated 5 years ago
- A small Lua formatter / pretty printer☆12Nov 25, 2020Updated 5 years ago
- Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK☆16Dec 2, 2018Updated 7 years ago
- WebGuard: Building a Generalizable Guardrail for Web Agents☆13Jul 28, 2025Updated last year
- This repository contains my implementation of the IKK attack as proposed by Islam et al. in their paper 'Access Pattern disclosure on Sea…☆10Dec 8, 2022Updated 3 years ago
- TJCS-Undergraduate-Courses☆112Jul 9, 2022Updated 4 years ago
- ☆12Oct 20, 2015Updated 11 years ago
- Nexys 4 DDR Artix-7☆12Jun 15, 2018Updated 8 years ago
- Project for CS101016 and CS100160, Tongji University. Use Verilog HDL to build a CPU.☆10Mar 20, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- TongjiUniversity的一些课程作业☆49Sep 2, 2024Updated 2 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆22Nov 26, 2018Updated 7 years ago
- 同济大学计算机组成原理31条指令CPU以及54条指令CPU实现（Verilog）☆16Jun 4, 2023Updated 3 years ago
- Source code for "Distraction-based Neural Models for Document Summarization" runnable on GPU and CPU.☆15May 22, 2018Updated 8 years ago
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Dec 14, 2020Updated 5 years ago
- AI agents that think must never act. Open-source security framework with composable modules for safe autonomous AI.☆14Jul 4, 2026Updated 3 months ago
- TJ 计算机系统实验: 89条指令CPU☆12Nov 11, 2024Updated last year
- a FPGA tank game for ZJU Digital logic design☆10Jan 17, 2021Updated 5 years ago
- 使用百度图像识别接口的微信小程序☆13Dec 23, 2022Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆35Aug 31, 2020Updated 6 years ago
- ACE: the Abstract-Concrete-Execute security architecture for LLM-integrated app systems.☆15Apr 21, 2026Updated 6 months ago
- 计算机网络 课程设计☆16Jan 2, 2024Updated 2 years ago
- Connecting FPGA and Arduino using SPI.☆25Apr 30, 2022Updated 4 years ago
- TJCS软工期末复习(曾国荪班)☆10Jul 2, 2024Updated 2 years ago
- 同济大学计算机部分作业，计算机系统实验（系统移植参考github上学长的代码），操作系统课程设计，数据库课程设计，web技术，编译原理（不包含两次实验，因为是小组作业hhh），操作系统，计算机系统结构（流水线CPU，静态的和动态的），计算机组成原理（包含31条MIPS单周期…☆137Mar 31, 2025Updated last year
- 龙芯官方给出的MIPS源码与我个人优化文件结构之后的源码☆15May 3, 2019Updated 7 years ago