Burijjibenzen / FPGA-Super-Mario-Bros
同济大学22级数字逻辑大作业
☆16Updated last month
Related projects ⓘ
Alternatives and complementary repositories for FPGA-Super-Mario-Bros
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆54Updated last year
- ☆65Updated last week
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆17Updated 5 months ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆24Updated 3 years ago
- ☆76Updated 2 months ago
- 【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。☆109Updated 4 years ago
- This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.☆55Updated 3 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆62Updated 2 years ago
- ☆43Updated 4 months ago
- 一生一芯的信息发布和内容网站☆123Updated last year
- 实现一个基础但功能完善的计算机系统,根据《自己动手写CPU》实现,开发板为Nexys4 DDR☆32Updated 8 months ago
- Verilog实现单周期非流水线32位RISCV指令集(45条)CPU☆35Updated 3 years ago
- FPGA Innovation Design Competition:RISC-V Processor-based Hardware and Software Design in PGL22G☆12Updated last year
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆15Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated 5 months ago
- CQU Dual Issue Machine☆34Updated 4 months ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆43Updated 11 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆36Updated last year
- An exquisite superscalar RV32GC processor.☆143Updated 6 months ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆135Updated 5 years ago
- FPGA实现各种小游戏,学习并快乐着☆61Updated 2 years ago
- 同济大学数字逻辑综合作业☆18Updated 10 months ago
- ☆32Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆45Updated 11 months ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆121Updated 4 months ago
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆15Updated 3 years ago
- CPU Design Based on RISCV ISA☆76Updated 5 months ago
- ☆21Updated last year
- A softcore microprocessor of MIPS32 architecture.☆39Updated 4 months ago