关于C语言的基础知识
☆53Mar 10, 2023Updated 2 years ago
Alternatives and similar repositories for C-knowledge
Users that are interested in C-knowledge are comparing it to the libraries listed below
Sorting:
- C++基础知识☆18Oct 19, 2022Updated 3 years ago
- VIVO camera☆16May 29, 2019Updated 6 years ago
- The patch for the kernel bug☆20May 13, 2025Updated 9 months ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Keyboard firmware for ESP32 microcontrollers☆32Oct 25, 2020Updated 5 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Example of CRUSH compression with optimal parsing using BriefLZ algorithms☆16Nov 1, 2023Updated 2 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- ☆11May 8, 2022Updated 3 years ago
- This is a tool to access excel file.It let you read&write excel by annotation.It support many custom method to change the excel style or …☆11Jan 13, 2023Updated 3 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- ☆21Jan 22, 2026Updated last month
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 5 months ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- ☆10Sep 11, 2016Updated 9 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- vue+cdn+element+axios+sass+ multi page.☆12Feb 20, 2019Updated 7 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- ☆12Jul 28, 2022Updated 3 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- 「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ☆10Aug 26, 2021Updated 4 years ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆18Oct 28, 2024Updated last year
- Implemented a two-level (L1 and L2) cache simulator in C++ with round robin eviction policy☆10Jan 4, 2017Updated 9 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- 一次对PuppeteerSharp(无头浏览器)的尝试☆13Apr 15, 2022Updated 3 years ago
- A set of macros and functions to make defining a C module easier☆11Sep 9, 2019Updated 6 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 11 months ago