aikodigital/teste-frontend-v4 external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

aikodigital/teste-frontend-v4

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/aikodigital/teste-frontend-v4)

Close

aikodigital / teste-frontend-v4View on GitHubMore

• External links
• Readme badge

Teste V4 para a vaga de desenvolvedor Frontend.

☆15Mar 7, 2025Updated last year

Alternatives and similar repositories for teste-frontend-v4

Users that are interested in teste-frontend-v4 are comparing it to the libraries listed below

• aikodigital / teste-backend-v3

  View on GitHub
  Teste V3 para a vaga de desenvolvedor Backend.
  ☆11Mar 7, 2025Updated last year
• freecores / pipelined_fft_256

  View on GitHub
  Pipelined FFT/IFFT 256 points processor
  ☆10Jul 17, 2014Updated 11 years ago
• freecores / ethernet_tri_mode

  View on GitHub
  10_100_1000 Mbps tri-mode ethernet MAC
  ☆10Jul 17, 2014Updated 11 years ago
• Mi-V-Soft-RISC-V / miv-rv32-bare-metal-examples

  View on GitHub
  ☆13Aug 7, 2025Updated 7 months ago
• riscvarchive / riscv-zfinx

  View on GitHub
  ☆12Feb 15, 2024Updated 2 years ago
• ultraembedded / altor32

  View on GitHub
  AltOr32 - Alternative Lightweight OpenRisc CPU
  ☆13Dec 17, 2015Updated 10 years ago
• efabless / ravenna

  View on GitHub
  32-bit RISC-V microcontroller
  ☆12Sep 11, 2021Updated 4 years ago
• freecores / ahb_master

  View on GitHub
  Generic AHB master stub
  ☆12Jul 17, 2014Updated 11 years ago
• elementum-games / shinobi-chronicles

  View on GitHub
  https://shinobichronicles.com
  ☆12Jan 31, 2026Updated last month
• qedsoftware / doxygen-demo

  View on GitHub
  Demonstration of using Doxygen to generate documentation for C++ code. Credits to Brent Nash.
  ☆13May 20, 2013Updated 12 years ago
• freecores / zpu

  View on GitHub
  ZPU - the worlds smallest 32 bit CPU with GCC toolchain
  ☆16Jul 17, 2014Updated 11 years ago
• freecores / divider

  View on GitHub
  Hardware Division Units
  ☆10Jul 17, 2014Updated 11 years ago
• NerdingAlaska / bb0.2

  View on GitHub
  bb0.2 lives here!
  ☆10Apr 15, 2022Updated 3 years ago
• Bryce-Readyhough / caravel_UNCC_MPW_1

  View on GitHub
  This is the Google/EFabless/Skywater Caravel submission of an Analog Spiking Neuron Circuit. The submission also includes a SONOS transis…
  ☆12Apr 21, 2023Updated 2 years ago
• harshilasu / Intel-4004-CPU-in-Verilog

  View on GitHub
  Arizona State University CSE320
  ☆12Mar 22, 2015Updated 10 years ago
• paripath / cdf

  View on GitHub
  Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
  ☆13Feb 13, 2020Updated 6 years ago
• TheOneKevin / icarusext

  View on GitHub
  iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.
  ☆11Mar 4, 2023Updated 3 years ago
• antmicro / f4pga-examples

  View on GitHub
  ☆12Sep 4, 2023Updated 2 years ago
• freecores / aes-128_pipelined_encryption

  View on GitHub
  AES-128 Encryption
  ☆10Jul 17, 2014Updated 11 years ago
• epiclabs-io / docker-oracle-xe-11g

  View on GitHub
  Dockerfile of Oracle Database Express Edition 11g Release 2
  ☆10Nov 6, 2023Updated 2 years ago
• freecores / sgmii

  View on GitHub
  SGMII
  ☆13Jul 17, 2014Updated 11 years ago
• chipforge / PearlRiver

  View on GitHub
  1st Testwafer for LibreSilicon
  ☆15May 24, 2019Updated 6 years ago
• freecores / i2cslave

  View on GitHub
  I2C Slave
  ☆14Jul 17, 2014Updated 11 years ago
• freecores / usb_phy

  View on GitHub
  USB 1.1 PHY
  ☆11Jul 17, 2014Updated 11 years ago
• vsdip / vsdsram

  View on GitHub
  An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…
  ☆14Jul 22, 2020Updated 5 years ago
• drone / drone_playground

  View on GitHub
  Helping get up to speed with drone via examples
  ☆11Feb 1, 2022Updated 4 years ago
• stephanemagnenat / osqoop

  View on GitHub
  Osqoop is an open-source oscilloscope
  ☆11Mar 4, 2018Updated 8 years ago
• pradeepsk13 / vsdsram_sky130_1.8V

  View on GitHub
  Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node
  ☆16Mar 31, 2021Updated 4 years ago
• BigEd / verilog-6502

  View on GitHub
  This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL
  ☆20Feb 16, 2013Updated 13 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_io

  View on GitHub
  IO and periphery cells for the GF180MCU provided by GlobalFoundries.
  ☆14Dec 3, 2022Updated 3 years ago
• XUANTIE-RV / opensbi

  View on GitHub
  ☆17Feb 11, 2026Updated 3 weeks ago
• freecores / reed_solomon_decoder

  View on GitHub
  Reed Solomon Decoder (204,188)
  ☆13Jul 17, 2014Updated 11 years ago
• CentOS / duffy

  View on GitHub
  CentOS CI provisioner
  ☆10Updated this week
• walkingtospace / MIPSR10K

  View on GitHub
  MIPS R10000 architecture simulator with C++
  ☆10Jun 8, 2023Updated 2 years ago
• Deepak42074 / vsdsram_sky130

  View on GitHub
  Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns
  ☆14Dec 8, 2020Updated 5 years ago
• PaddingtonTheBear / dakimbo

  View on GitHub
  ☆14Jan 12, 2023Updated 3 years ago
• AlmaLinux / albs-node

  View on GitHub
  AlmaLinux Build System build node.
  ☆12Nov 15, 2025Updated 3 months ago
• lipro / tv80

  View on GitHub
  The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)
  ☆10Jan 9, 2016Updated 10 years ago
• freecores / fpu_double

  View on GitHub
  FPU Double VHDL
  ☆12Jul 17, 2014Updated 11 years ago