Data Structures and Algorithm Analysis in C
☆13May 10, 2018Updated 7 years ago
Alternatives and similar repositories for Structure
Users that are interested in Structure are comparing it to the libraries listed below
Sorting:
- To be the best unofficial Instagram app☆10Oct 17, 2015Updated 10 years ago
- Sample Gallery with RxJava☆14May 4, 2017Updated 8 years ago
- 微客工作室 for Android☆18Jun 21, 2016Updated 9 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- 项目资料总结☆11Mar 7, 2016Updated 9 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Provides useful subclasses from Support Library that work with Data Binding.☆33Mar 21, 2016Updated 9 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- ☆11May 8, 2022Updated 3 years ago
- port MaxRAMPercentage to Golang, adjust GC parameters(SetGCPercent/SetMemoryLimit) based on the target memory usage percentage, optimize …☆11Nov 25, 2024Updated last year
- 用jqueryMobile开发的手机可视化 监控管理系统☆10Oct 21, 2014Updated 11 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 5 months ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Data Structures and Algorithms lab repository☆11Jun 23, 2015Updated 10 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Build and train a working model to classify violence behavior on the sequence of frames, with use of recurrent neural networks, optical f…☆13Jun 25, 2022Updated 3 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Implemented a two-level (L1 and L2) cache simulator in C++ with round robin eviction policy☆10Jan 4, 2017Updated 9 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- Tutorial of Face Detection using OpenVino python☆11Nov 23, 2020Updated 5 years ago
- 适合用作输入货币的EditText。该控件处理了货币输入逻辑中的棘手问题。☆12Jul 3, 2015Updated 10 years ago
- ☆26Sep 28, 2025Updated 5 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- A sample wrapper application for Evolve. See https://github.com/VivekPanyam/Evolve☆21Nov 7, 2014Updated 11 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆16Feb 17, 2026Updated 2 weeks ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago