Implementations of the Simon and Speck Block Ciphers
☆102Jul 21, 2018Updated 7 years ago
Alternatives and similar repositories for Simon_Speck_Ciphers
Users that are interested in Simon_Speck_Ciphers are comparing it to the libraries listed below
Sorting:
- Reference code for the Simeck family of block ciphers☆15Jun 21, 2015Updated 10 years ago
- Speck Block Cipher Implementation☆15Nov 20, 2015Updated 10 years ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 5 years ago
- Fast implementations of the SIMON and SPECK lightweight block ciphers for the SUPERCOP benchmark toolkit. #nsacyber☆50Jun 13, 2018Updated 7 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Verilog VPI VGA Simulator using SDL☆11Feb 9, 2015Updated 11 years ago
- ☆12May 29, 2020Updated 5 years ago
- VHDL related news.☆27Mar 2, 2026Updated last week
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…☆13Mar 1, 2026Updated last week
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated last week
- Xilinx Bitstream Format Library. Easily read .bit files from C programs.☆14Nov 16, 2015Updated 10 years ago
- Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)☆16Dec 24, 2020Updated 5 years ago
- read HN from the command line☆15Sep 2, 2015Updated 10 years ago
- Simple alarm clock program; also a demonstration of andlabs/ui.☆53Jul 4, 2014Updated 11 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- ☆33Apr 30, 2023Updated 2 years ago
- masked, bit-sliced AES-128 demo code☆14Jan 10, 2025Updated last year
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- A hardware model checker for hyperproperties☆18Jun 14, 2024Updated last year
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- Code for FSE 2020 - Improving the MILP-based Security Evaluation Algorithm against Differential-Linear Cryptanalysis Using A Divide-and-C…☆16Dec 16, 2019Updated 6 years ago
- d☆14Sep 5, 2025Updated 6 months ago
- VHDL plugin for RgGen☆15Jan 7, 2026Updated 2 months ago
- A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.☆42Nov 17, 2014Updated 11 years ago
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆20Jun 4, 2020Updated 5 years ago
- Malware analyses and helpful scripts☆29May 26, 2022Updated 3 years ago
- fbtftp is Facebook's implementation of a dynamic TFTP server framework☆15Feb 24, 2019Updated 7 years ago
- Multi-function, universal, fixed-point CORDIC☆15Feb 20, 2022Updated 4 years ago
- UEFI bootkit: Hardware Implant. In-Progress☆15Mar 7, 2022Updated 4 years ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 3 years ago
- Sparkle, Schwaemm and Esch: Lightweight Symmetric Cryptography for the Internet of Things☆36Feb 22, 2023Updated 3 years ago
- A micro-kernel operating system based on the Barrelfish CPU-driver.☆21Mar 6, 2018Updated 8 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Feb 12, 2026Updated 3 weeks ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Nov 29, 2017Updated 8 years ago