coreboot / libgfxinitLinks
mirror of https://review.coreboot.org/libgfxinit.git
☆24Updated 3 weeks ago
Alternatives and similar repositories for libgfxinit
Users that are interested in libgfxinit are comparing it to the libraries listed below
Sorting:
- OpenFirmware as used on OLPC (and elsewhere)☆123Updated 9 years ago
- GCC port for OpenRISC 1000☆26Updated 9 months ago
- A set of utilities to process FCODE, OpenFirmware's byte code☆36Updated 3 weeks ago
- Open Firmware (IEE1275-1994) implementation by its inventor.☆78Updated 3 years ago
- RISCV port of the Slackware distribution☆12Updated 4 years ago
- Sun's OpenBoot implementation of OpenFirmware☆66Updated 9 years ago
- Slimline Open Firware - an implementation of IEEE1275 Open Firmware for some POWER ISA systems☆41Updated 6 months ago
- RTOS based on L4 microkernel.☆18Updated 7 years ago
- Solaris/PPC☆21Updated 11 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆60Updated 5 years ago
- This is a portable, open source emulator of the 32-bit Inmos T414/T800/T801/T805 Transputer family, and a host/file I/O Server that inter…☆21Updated last week
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆39Updated 5 years ago
- ☆18Updated 5 years ago
- Allwinner SoC support for the Genode OS framework☆17Updated 3 weeks ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆54Updated 4 years ago
- Mostly AVR compatible FPGA soft-core☆29Updated 4 years ago
- Website for stories around the Genode operating system (migrated to codeberg.org)☆18Updated 3 weeks ago
- Collection of community-maintained components for Genode☆50Updated this week
- An example in bare metal RV32 assembly for the longan nano board☆21Updated 4 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- Bare-metal Forth implementation for RISC-V☆59Updated last year
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated 2 years ago
- Forth for RISC-V SBCs☆33Updated 5 months ago
- iCE40HX8K development board with SRAM and bus for fast ADC, DAC, IOs☆39Updated last year
- Codegen's SmartFirmware implementation of OpenFirmware☆33Updated 9 years ago
- 64-bit MISC Architecture CPU☆13Updated 9 years ago
- A bit-serial CPU☆19Updated 6 years ago
- J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.☆28Updated 5 years ago
- ☆61Updated 2 years ago
- eForth for the j1 simulator and actual J1 FPGAs☆38Updated 10 years ago