Build universally compatible python packages from a substantial subset of Python 3.8.
☆21Aug 8, 2022Updated 3 years ago
Alternatives and similar repositories for lib3to6
Users that are interested in lib3to6 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Experimentations with distributed tasks for a game engine☆12Jul 20, 2012Updated 14 years ago
- The Go programming language, modified to emit warnings☆21Aug 13, 2020Updated 5 years ago
- Image-space Warping library, implementing scatter-based warping, bidirectional gather-based warping and forward-only gather-based warping…☆16Apr 10, 2026Updated 3 months ago
- A project demonstrate how to config ad9361 to TX mode☆13Dec 9, 2018Updated 7 years ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- A language where you only implement comments☆21Apr 5, 2024Updated 2 years ago
- Rust Bindings for CRIU☆27Updated this week
- ☆21Dec 11, 2022Updated 3 years ago
- delphi7-lite 单文件版本☆12Jun 22, 2020Updated 6 years ago
- [OBSOLETE] The recipe is now in https://github.com/bincrafters/community☆13Nov 14, 2020Updated 5 years ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- mechatronics firmware☆15Jun 10, 2026Updated last month
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Plugin for Stencil (https://stenciljs.com) to output a proxy module to consume web components with type safety in Elm☆21Feb 12, 2024Updated 2 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- A picorv32 RISC-V processor with some very simple memory and peripherals. For Terasic DE-0 Nano☆13Apr 15, 2019Updated 7 years ago
- petiger的版本发布☆12Dec 3, 2020Updated 5 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated 2 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- Template for a simple elm-land, lamdera and google auth start up☆20Nov 15, 2023Updated 2 years ago
- ☆11Oct 18, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 4 months ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- The source code for the XTRX FPGA image☆17Nov 19, 2022Updated 3 years ago
- C#版本的word,excel操作程序☆11Dec 4, 2015Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 10 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- SystemVerilog code for image processing tasks like demosaicing☆11Jun 28, 2020Updated 6 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆15Jun 1, 2017Updated 9 years ago
- Headless wayland browser vnc sessions in a container☆30Jul 17, 2025Updated last year
- small fastcdc implementation in c99☆18Dec 31, 2022Updated 3 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago