High-level C++ for Accelerator Clusters
☆156Sep 2, 2026Updated 2 weeks ago
Alternatives and similar repositories for celerity-runtime
Users that are interested in celerity-runtime are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Synchronous, single-threaded, library-only SYCL implementation for debugging and verification.☆40Aug 11, 2026Updated last month
- SYCL Conformance Tests☆76Sep 10, 2026Updated last week
- Compiler for multiple programming models (SYCL, C++ standard parallelism, HIP/CUDA) for CPUs and GPUs from all vendors: The independent, …☆1,938Updated this week
- A pseudo random number generator library written against the SYCL API.☆11Jun 11, 2019Updated 7 years ago
- SYCL Open Source Specification☆158Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- List all available information about all SYCL devices and platforms☆15Sep 14, 2020Updated 6 years ago
- Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects.☆18Feb 17, 2021Updated 5 years ago
- Archived implementation of BLAS using the SYCL open standard. See oneMath for a replacement.☆259Jan 13, 2025Updated last year
- SYCL Benchmark Suite☆68Jun 22, 2025Updated last year
- Abstraction Library for Parallel Kernel Acceleration☆426Updated this week
- Collection of samples and utilities for using ComputeCpp, Codeplay's SYCL implementation☆326Aug 11, 2023Updated 3 years ago
- OpenCL/SPIR-V implementation of HIP☆105Nov 9, 2022Updated 3 years ago
- SYCL Academy, a set of learning materials for SYCL heterogeneous programming☆542Aug 6, 2026Updated last month
- Public proposals, extensions, information and materials from the SYCL working group☆15Jan 26, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Open Source Parallel STL implementation☆529Jan 26, 2024Updated 2 years ago
- SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM☆124Nov 4, 2024Updated last year
- A High-Throughput Parallel Lossless Compressor for Scientific Data☆76Jan 22, 2023Updated 3 years ago
- [DEPRECATED] Moved to ROCm/rocm-libraries repo